In dynamic random access memory (DRAM) integrated circuit devices, DRAM cell arrays are typically arranged in rows and columns such that a particular DRAM cell is addressed by specifying its row and column within the array. A wordline connects a row of cells to a set of bitline sense amplifiers that detect the data in the cells. In a read operation, a subset of the data in the sense amplifiers is then chosen, or “column-selected” for output. DRAM cells are “dynamic” in the sense that the stored data, typically in the form of charged and discharged storage capacitors, will dissipate after a relatively short period of time. Thus, in order to retain the information, the contents of the DRAM cells must be refreshed. The charged or discharged state of the storage capacitor must be reapplied to an individual memory cell in a repetitive manner. The maximum amount of time allowable between refreshing operations is determined by the charge storage capabilities of the capacitors that make up the DRAM cell array. DRAM manufacturers typically specify a refresh time for which it guarantees data retention in the DRAM cells.
A refresh operation is similar to a read operation, but no data is output. The sensing of the data in the cells by the sense amplifiers is followed by a restoring operation that results in the data being rewritten to the cells. The data is, thus, “refreshed”. The refresh operation is performed by enabling a wordline according to a row address, and enabling a sense amplifier. In addition, the refresh operation may be carried out by operating the sense amplifier without receiving an external refresh address. In this case, a refresh address counter that is integrated in a DRAM chip generates a row address subsequent to receiving an external start address.
Refresh operation is categorized as “auto-refresh” and “self-refresh”. The auto-refresh operation occurs when, during operation of the chip, a refresh command is periodically generated and received. During the auto-refresh, the receipt of other commands to the chip is interrupted and refresh is carried out. Then, the chip is allowed to receive and act on the other commands. The self refresh function is one for performing refresh operations within the DRAM when in a standby mode to retain the data written in its memory cells.
In order to perform the self-refresh operation, regular internal reading of cell data and rewriting that data are established in order to prevent data losses when the chip is operating in a so-called “sleep” mode. An internal timer controls the frequency of self-refresh. The self-refresh control circuitry is comprised of an internal oscillator, a frequency divider and a refresh count request block. Temperature monitoring and variable refresh rate control circuitry can be included. In known dynamic DRAM integrated circuits having a self-refresh function, an operation mode is automatically switched to a self-refresh mode to perform self-refresh when required.
U.S. Pat. No. 4,636,989 granted to Ikuzaki on Jan. 13, 1987 discloses a dynamic MOS random access memory having an automatic refresh circuit. In the memory, a clock generator generates refresh clock pulses when the address strobe signal is not produced. U.S. Pat. No. 5,365,487 granted to Patel et al. on Nov. 15, 1994 discloses a DRAM with self-refresh management. U.S. Pat. No. 5,862,093 granted to Sakakibara on Jan. 19, 1999 discloses a dynamic memory device with refreshing timing signals generated to detect the relevant time to perform self-refresh.
In order to obtain high-speed operation and high-density integrated circuits, deep sub-micron CMOS processes like 90 nm, 65 nm, 45 nm have been introduced and implemented in many semiconductor IC devices. For those deep sub-micron processes, MOS transistors are scaled down (i.e., have minimum transistor dimensions decreased) and threshold voltage Vth of the transistors are lowered. However, the lowered threshold voltage results in significant sub-threshold leakage (i.e., leakage current present for transistor gate voltages below a threshold voltage) and therefore, semiconductor ICs based on such lowered threshold voltages consume more power in normal operation as well as in a power saving mode of operation. Since a DRAM cell includes a minimally sized access transistor for coupling the storage capacitor to a bitline, the stored charge can quickly leak from the storage capacitor. Therefore, more frequent “self-refresh” operations are required.
Semiconductor integrated circuits (ICs) are becoming smaller to accommodate more transistors in a single chip and to achieve faster operating speeds. However, smaller and faster CMOS type transistors have higher leakage currents and this leakage current issue is becoming a serious design challenge in nanometer technology devices. To reduce standby power consumption of DRAM devices, a “sleep” mode is provided from external DRAM control logic. In the “sleep” mode, DRAM cells are required to be “refreshed” periodically in order to retain cell data. This is accomplished using “self-refresh”. However, smaller and faster CMOS transistors have significant leakage problems, resulting in the requirement for more frequent “self-refresh” operations than older DRAM technologies having lower leakage current issues. Even more seriously, most embedded DRAM macros (DRAM memory circuit blocks used in larger system-on-chip applications) fabricated with a sub-100 nm logic process require very frequent “self-refresh” because of the small cell capacitance values in certain worst case conditions, like high temperatures, very fast transistor process and very high power supply level, etc. This process, voltage and temperature (PVT) combination can easily vary during the manufacturing and/or device operation period. Therefore, the internal self-oscillator for the self-refresh signal generation should be able to cover a wide range of DRAM cell retention times due to PVT variations.
The variable range of DRAM cell retention time may fall between a few microseconds and few milliseconds if the process technology moves to 45 nm or less. Accordingly, upon receipt of a self-refresh mode entry request, the internal oscillator for self-refresh has to be initialized to generate the self-refresh signal in a very short period of time. The self-refresh signal must be produced to properly perform self-refresh for the shortest possible cell retention time (e.g., microsecond order) and also be maintained for the longest possible cell retention time (e.g., millisecond order) for long periods of reliable oscillation characteristics. It is, thus, sought for DRAM devices to perform and achieve reliable self-refresh, even though the cell retention time is variable across a wide range.